Free tool · PCIe Gen4 · Gen5 · Gen6

MCIO / SlimSAS Cable Length & Insertion Loss Calculator

Add up a PCIe channel the way the specifications do: host package, board trace, connectors, cable and the card at the far end, against the 28, 36 or 32 dB the generation allows at its Nyquist frequency. The result is the margin left, a pass, marginal or fail call, and the longest passive cable the rest of your channel leaves room for. Every default is a published figure, listed with its source below, and every one of them can be overwritten with your own data.

Link

Nyquist 16 GHz; channel budget 36.0 dB. The package, card and connector figures below follow the generation unless you change them.

SNIA SFF-TA-1016. The loss is per lane, so 4i and 8i read the same.

One passive channel from the host package to the device.

Cable

Preset 0.06 dB/cm at 16 GHz, raw twinax. Sources in the method table.

dB/cm

Raw cable at 16 GHz; type the figure from your cable's datasheet or S-parameters to override the preset.

cm
Length unit
pairs

Two for a straight cable, one at each end. Add one for every adapter or extension in the path.

dB

SFF-TA-1016 allows 1 dB per mated pair up to 16 GHz; the figure includes the termination on both sides.

Host board
in

Stripline from the package to the cable connector. Breakout from a large BGA often needs about 5 in.

dB/in

Stripline at 16 GHz. Your fabricator's test coupon beats any preset.

dB

AC coupling capacitors, vias and the connector breakout on the host board.

dB

The root complex package in the PCIe 5.0 CEM split.

Far end

The cable lands on a riser that carries a CEM slot, and an add-in card plugs into it. The slot connector is added to the sum.

dB

About an inch of riser trace at the low-loss figure. The slot connector is the CEM allowance, 1.5 dB.

dB

The CEM allowance for the card-edge connector.

dB

The PCIe 5.0 CEM add-in card budget, package included. A drive or card with its own figure goes here instead.

Method

How it is calculated

The channel is summed segment by segment at the generation's Nyquist frequency, the way the specifications budget it, and compared with the total the generation allows. Losses in decibels add, so the sum is a plain addition; the work is in the figures that go into it.

channel loss = host package
             + trace length × board loss per inch
             + vias, caps & breakout
             + mated pairs × loss per pair
             + cable length × cable loss per cm
             + far-side board (+ slot connector, on a riser)
             + end device, or the retimer's package

margin       = budget − channel loss
verdict      = pass      if margin ≥ 10 % of the budget
               marginal  if 0 ≤ margin < 10 %
               fail      if margin < 0

longest cable, recommended = (0.9 × budget − everything but the cable) ÷ cable loss per cm
longest cable, absolute    = (budget − everything but the cable) ÷ cable loss per cm

With a retimer the budget restarts on each side of it, so the sum covers only the side the cable is on: from the retimer's package to the device when it sits on the host board, from the host package to the retimer's package when it sits on the far board. The 10 % design margin is the low end of the 10 to 20 % that practice keeps for temperature, humidity, reflections, crosstalk and supply noise [15].

Default values, and where each comes from

Every default below can be overwritten in the form. The numbers in brackets point to the sources at the end of the page.

SegmentPCIe 4.016 GT/s, 8 GHzPCIe 5.032 GT/s, 16 GHzPCIe 6.064 GT/s, 16 GHzSource
Channel budget, bump to bump28.0 dB36.0 dB32.0 dB[1][2][3]
Root complex package5.0 dB9.0 dB6.3 dB[1][7][3]
CEM slot connector1.5 dB1.5 dB1.5 dB[1][7]
Add-in card, edge to die8.0 dB9.5 dB8.5 dB[1][3][12]
Vias, AC caps & breakout1.0 dB1.5 dB1.5 dB[7]
Non-root package (used for a retimer)4.2 dB4.2 dB4.6 dB[2][3]
Cable, 30 AWG twinax, per cm0.039 dB0.060 dB0.060 dB[8][2][16]
Cable, 32 AWG twinax, per cm0.044 dB0.070 dB0.070 dB[9][7]
Cable, 34 AWG twinax, per cm0.055 dB0.079 dB0.079 dB[7][10][4]
Board, Ultra-low-loss (Megtron 7, Tachyon 100G class), per inch0.55 dB0.90 dB0.90 dB[4][2]
Board, Low-loss (Megtron 6 class), per inch0.70 dB1.20 dB1.20 dB[7][2]
Board, Mid-loss (FR408HR, I-Speed class), per inch0.85 dB1.40 dB1.40 dB[10][2]
Board, Standard FR-4 (Loss tangent 0.02), per inch1.20 dB2.00 dB2.00 dB[2]
MCIO mated pair (SNIA SFF-TA-1016)1.0 dB per pair, either frequency[5][2][11]
SlimSAS mated pair (SNIA SFF-8654)1.0 dB per pair, either frequency[6][20]
Far-side board, Backplane or device board2.5 dB[11]
Far-side board, Riser or paddle card with a PCIe slot1.0 dB[1][7]

What the presets rest on

30 AWG cable
Samtec's 85 Ω 30 AWG FEP twinax datasheet curve reads about 6 dB per metre at 16 GHz and 3.9 dB at 8 GHz; the DesignCon 2023 measurements of Gen5 MCIO cables average about 0.06 dB/cm. A 2017 3M catalogue puts its 30 AWG at 7.2 dB per metre at 12.89 GHz, so a given cable can sit a third higher. [8][2][16]
32 AWG cable
Samtec's 32 AWG datasheet curve reads about 6.5 dB per metre at 16 GHz and 4.4 dB at 8 GHz, for a 100 Ω cable; an 85 Ω PCIe cable of the same gauge loses a little more, so the preset is rounded up. [9][7]
34 AWG cable
Samtec states 0.20 dB per inch at 16 GHz for 34 gauge twinax (0.079 dB/cm); its PCIe 6.0 article gives 0.15 to 0.20 dB per inch depending on gauge, and PCI-SIG's cabling talk uses about 0.19 dB per inch. The 8 GHz value is scaled from 16 GHz. [7][10][4]
Ultra-low-loss board
PCI-SIG's cabling talk uses about 1 dB per inch at 16 GHz for ultra-low-loss board; the DesignCon 2023 paper's reference for Tachyon 100G stripline is 0.85 dB per inch. [4][2]
Low-loss board
Samtec budgets 1.1 dB per inch at 16 GHz on low-loss material; the DesignCon 2023 paper measured 1.2 to 1.5 dB per inch on stripline with a loss tangent of 0.002 to 0.004. [7][2]
Mid-loss board
Samtec's PCIe 6.0 article puts mid-range dielectrics as high as 1.4 dB per inch at 16 GHz; the DesignCon 2023 paper's reference for FR408HR stripline is 1.33. [10][2]
Standard FR-4 board
A rule of thumb, not a measurement: standard FR-4 is a Gen1 to Gen3 material and no source quotes it at 16 GHz; the DesignCon paper's microstrip measurements on mid-loss board ran 2 to 4 dB per inch. [2]
Gen4 board figures
The 8 GHz presets follow the 16 GHz figures scaled for frequency; Samtec's own Gen4 example uses 1.35 dB per inch for mid-range material, the conservative end. [7]
MCIO connectors
SFF-TA-1016 limits a mated connector pair to 1 dB up to 16 GHz for every line rate it lists, 32 GT/s included. Measured harnesses agree: the DesignCon 2023 paper's 1 m cable with both connectors came to 8 dB against 6 dB of bare cable, and NVIDIA's 250 mm MCIO harness measures 3.5 dB with its connectors. [5][2][11]
SlimSAS connectors
SFF-8654 is a mechanical specification: its electrical speed requirements were removed in Rev 1.0 and it names SAS as its application, so there is no published loss limit. The tool assumes the MCIO figure; replace it with your connector maker's data. [6][20]
PCIe 4.0 split
Samtec's 2021 example budgets the Gen4 connector at 0.5 dB; the tool keeps PCI-SIG's 1.5 dB. The non-root package figure is the Gen5 reference, used as a conservative stand-in. [1][7]
PCIe 6.0 split
The paper splits 32 dB into 8.5 dB for the add-in card (4.6 dB of it package) and about 15.7 dB for the host board traces. The 7.8 dB left is the root package and the slot connector together; the tool keeps the connector at 1.5 dB and gives the package the rest. [3][12]
A figure often quoted that is not used
NVIDIA's BlueField-3 guide gives 0.24 dB/cm for a harness with its connectors. That harness is a Cabline CA-II Plus micro-coax assembly, not an MCIO twinax cable, and its own table works out to about 0.19 dB/cm plus a dB for the two ends. NVIDIA's MCIO figure is the ConnectX-8 one: 3.5 dB for a 250 mm harness with both connectors, which the defaults here reproduce within half a decibel. [13][11]

Disclaimer. Estimates only. Insertion loss is one of several things that decide whether a link trains and holds its rate; return loss, crosstalk, skew and equalization are not modeled, and real cables vary by lot and by vendor. Validate a design with S-parameter measurement of the actual assembly and channel, and treat this as a budget check, not a compliance result.

Why quoted maximum lengths differ

A cable never gets a budget of its own. PCIe budgets the whole channel, 36 dB at 16 GHz for Gen5, and the cable gets whatever the host package, the board trace, the connectors and the card at the far end leave over. Move the CPU an inch further from the connector or change the laminate, and the length that fits changes with it, before anyone has touched the cable.

That is why a retimer card maker can write that passive Gen5 MCIO hits a wall at 30 cm, a cable maker can quote 0.5 to 0.75 m, a connector maker can promise over a metre, and PCI-SIG's internal cable specification can allow 1 m. Each describes a different host board, a different margin policy, or no measurement at all. The three channels below differ only in the host trace and span all of those answers.

Cables also differ among themselves. The DesignCon 2023 measurements found one of four vendors at twice the loss of the others, and a 100 Ω twinax datasheet reads a little better than the 85 Ω cable a PCIe assembly is built from. Ask the cable maker for insertion-loss data at 16 GHz, or for the Touchstone files, and put that figure in the cable field here instead of the preset.

Host boardChannelWhat fitsLoad
Short host trace2 in of ultra-low-loss board from the CPU to the MCIO connector, 30 AWG cable, a backplane at the far end.About 1 m of cable keeps 10 % margin. This is the channel behind the one-metre claims and the CopprLink limit.Open →
Typical host trace5 in of low-loss board, otherwise the same.About 32 cm keeps 10 % margin; about 92 cm uses the whole budget. Both the 30 cm and the 1 m camps can point at this board.Open →
Long host trace7 in of mid-loss board, otherwise the same.No passive length keeps 10 % margin and about 28 cm uses the whole budget. This board needs a retimer, whatever the cable.Open →

When you need a retimer, and where

When the sum is over the budget, or inside it with less than about 10 % to spare, a passive cable will not be made to work by buying a better one: the trace and packages are fixed costs. The usual symptom is a link that trains at the next generation down or logs correctable errors, not one that fails outright.

A retimer is a full PCIe receiver and transmitter in the path, so the budget starts again on each side of it: the channel from the CPU to the retimer and the channel from the retimer to the device are each checked against the full figure, and a link may carry two of them. A redriver only amplifies, is not defined by the PCIe base specification, and does not reset the budget.

Two placements are common. On the host board next to the cable connector, the retimer pays for a long CPU-to-connector trace, and the cable channel starts fresh. On the far board, right after the cable, it pays for the cable and leaves a short channel to the device. The retimer option above models either, charging the retimer's own package loss to the channel it terminates.

30, 32 or 34 AWG

Thinner wire loses more: at 16 GHz the presets run from about 0.06 dB/cm for 30 AWG to about 0.08 dB/cm for 34 AWG, a third more loss for the same length. The reason to accept it is bundle size: a 34 AWG pair is thinner and lighter, and an 8i or 16i harness of them routes through a dense chassis that a 30 AWG bundle will not.

Impedance matters too. PCIe cables are 85 Ω nominal, and a 100 Ω twinax of the same gauge loses a little less per metre, so a datasheet curve for a 100 Ω part is slightly optimistic for the 85 Ω cable in an MCIO assembly. The presets are rounded with that in mind.

Gauge sets the slope; connectors set the offset. Two mated MCIO pairs cost about as much as 30 cm of 30 AWG cable, which is why a short cable is never free and why a cable-to-cable adapter costs as much as another third of a metre.

FAQ

Common questions

Is this calculator vendor-neutral?

Yes. It models no vendor's product. The defaults come from the PCIe CEM budgets, the SNIA connector specifications, two public cable datasheets, one conference paper and NVIDIA's published channel measurements, each listed under Sources with what was taken from it. Every default can be replaced with your own figure, and the link you share carries your values.

My cable vendor says 1 m works at Gen5. Why does the calculator say 30 cm?

Because the two of you are describing different host boards. The vendor's metre fits a short, low-loss trace from the CPU to the connector; the calculator's 30 cm is what a 5 in trace on low-loss board leaves over once 10 % margin is kept. Put in your own trace length and material, and if the vendor measured the cable, put in that loss too.

Does choosing SlimSAS instead of MCIO change the loss?

Not in this model: a mated pair of either is budgeted at 1 dB, and the cable behind it is the same twinax. What differs is what the connector is specified for. SFF-TA-1016 publishes a 1 dB mated-pair limit to 16 GHz; SFF-8654 publishes no signal-integrity limit at all, and connector makers position SlimSAS at PCIe 4.0 and 5.0. At 32 GT/s and above, use an MCIO assembly or a SlimSAS assembly its maker has qualified at that rate.

Does 4i versus 8i, or x8 versus x16, change the result?

No. The budget is per lane, and an 8i connector is two 4-lane groups side by side; a 16i cable is two 8i groups. Lane count changes the harness, not the loss of any one lane, so the calculator does not ask for it beyond the connector type.

Can I use it for PCIe 6.0?

Yes. PCIe 6.0 doubles the data rate with PAM4 at the same 16 GHz Nyquist frequency, so the cable loss figures are the ones Gen5 uses; the budget drops to 32 dB and the add-in card to 8.5 dB. PAM4 is less tolerant of reflections and crosstalk than NRZ, and this tool does not model either, so keep more margin, not less.

Why is a pass not a guarantee?

Because insertion loss is one line of a channel analysis. Return loss, crosstalk, skew, the equalization the devices can apply and the real package losses all move the result, and the specifications settle compliance with S-parameters and statistical eye simulation, not a sum. Use the pass to decide what is worth building and measuring, and measure it.

Sources

Where the numbers come from

Each entry says what the calculator takes from it. Two of them are vendor claims quoted for what they are, the conflicting length figures the page explains, not figures the tool uses.

  1. [1]PCI Express 5.0 Architecture Channel Insertion Loss Budget — Astera Labs, written for PCI-SIG, 2020.The CEM budget table: 22 / 28 / 36 dB for Gen3 / Gen4 / Gen5 and its split into root package, CEM connector, add-in card and system board; 16 GHz as the Gen5 Nyquist frequency.
  2. [2]PCIe Gen5 Signal Integrity Implementation – Issues & Solutions — D. Telian, K. Rowett, I. Teplitsky, DesignCon 2023, 2023.Measured Gen5 MCIO cable loss of about 0.06 dB/cm at 16 GHz across 36 cables from four vendors; a 1 m cable with connectors at 8 dB; stripline at 1.2 to 1.5 dB per inch; the 36 dB budget (Base Spec Table 8-8), the 8.4 dB root and 4.2 dB non-root reference packages.
  3. [3]How the Doubling of Interconnect Bandwidth with PCI Express 6.0 Impacts IP Electrical Validation — D. Bouse (Tektronix), M. Sanyal (Synopsys), white paper, 2022.The PCIe 6.0.1 budget of 32 dB at 16 GHz, split about 23.5 dB to the root-complex side and 8.5 dB to the add-in card (4.6 dB of it package), leaving about 15.7 dB for host board traces.
  4. [4]PCIe Cabling Solutions for Next Generation AI, HPC, and Storage Applications — M. Mazumder (Intel; co-chair, PCI-SIG Electrical WG), SNIA SDC 2024, 2024.CopprLink internal cables (SFF-TA-1016) to 1 m and external (SFF-TA-1032) to 2 m at 32 and 64 GT/s; board loss about 1 dB per inch and cable about 0.19 dB per inch at 16 GHz; cable assemblies 85 Ω nominal.
  5. [5]SFF-TA-1016 Rev 1.3, Internal Unshielded High Speed Connector System — SNIA SFF TA TWG, 2024.Table 9-1: a mated connector pair loses no more than 1 dB up to 16 GHz at 25, 28 and 32 GT/s NRZ and 56 GT/s PAM4; cable assembly limits are left to the application specification.
  6. [6]SFF-8654 Rev 1.2, 0.6mm 4/8X Unshielded I/O Connector — SNIA SFF TA TWG, 2018.The SlimSAS connector's scope: a mechanical specification meeting the internal I/O requirements of T10 SAS, its speed characteristics removed in Rev 1.0.
  7. [7]Successful PCIe Interconnect Guidelines at 8, 16, and 32 GT/s — S. Krooswyk, Samtec gEEk spEEk, 2021.One inch of 34 gauge twinax is 0.20 dB at 16 GHz; a worked budget for Gen3/4/5 with board at 0.8 / 1.35 / 1.1 dB per inch, vias and capacitors at 0.5 / 1 / 1.5 dB and the add-in card at 6.5 / 8.5 / 9.5 dB.
  8. [8]TTF-3085CU, 85 Ω 30 AWG micro twinax cable datasheet — Samtec, 2026.The 1 m insertion-loss curve: −3 dB at 5.2 GHz, about −6 dB at 16 GHz and about −3.9 dB at 8 GHz, read from the plot.
  9. [9]TTF-32100, 100 Ω 32 AWG micro twinax cable datasheet — Samtec, 2026.The 1 m insertion-loss curve: −3 dB at 4 GHz, −7 dB at 18 GHz, about −6.5 dB at 16 GHz and about −4.4 dB at 8 GHz, read from the plot.
  10. [10]How To Choose an Interconnect for PCIe 6.0 High-Speed Systems — S. Krooswyk, A. Fellbaum, M. Burns (Samtec), Signal Integrity Journal, 2023.The channel target reduced from 36 to 32 dB for PCIe 6.0; twinax at 0.15 to 0.20 dB per inch at 16 GHz depending on gauge; mid-range board as high as 1.4 dB per inch; a 1 m cable with 3 in of host and 4 in of card trace.
  11. [11]ConnectX-8 SuperNIC User Manual: Channel Insertion Loss — NVIDIA, 2026.Measured at 16 GHz: the MCIO harness with its connectors 3.5 dB, the passive auxiliary card 2.5 dB, the card's own lanes 5 dB, 11 dB in all; add 0.5 dB for variation. The kit's cable is 250 mm (the auxiliary kit page).
  12. [12]ConnectX-9 SuperNIC User Manual: Channel Insertion Loss — NVIDIA, 2026.The PCI-SIG-approved add-in card total of 8.5 dB at 16 GHz in a PCIe 6.0 design, with the same 3.5 dB MCIO harness.
  13. [13]BlueField-3 Networking Platform User Guide: Channel Insertion Loss — NVIDIA, 2026.What the often-quoted 0.24 dB/cm is: a Cabline CA-II Plus micro-coax harness (3.8 / 7.6 / 11.4 dB at 15 / 35 / 55 cm with connectors), not an MCIO twinax cable. Also the 36 dB budget and the 9.5 dB add-in card.
  14. [14]FAQs: PCIe Retimers — Astera Labs, 2026.A retimer supports the full channel budget on each side and the loss is budgeted per side; at most two retimers in a link; a redriver amplifies while a retimer retransmits a fresh copy of the signal.
  15. [15]How to Manage the PCIe 5.0 Channel Insertion Loss Budget — L. Liu (Astera Labs), Electronic Design, 2023.Keep 10 to 20 % of the budget as margin, 4 to 7 dB at Gen5, for temperature, humidity, reflections, crosstalk and supply noise.
  16. [16]3M Twin Axial Cable Assemblies (catalogue) — 3M, 2017.An 85 Ω 30 AWG twinax measured at 5.0 dB per metre at 8 GHz and 7.2 dB per metre at 12.89 GHz: the lossier end of the 30 AWG range.
  17. [17]PCI-SIG Announces CopprLink Cable Specifications for PCIe 5.0 and 6.0 Technology — PCI-SIG press release, Business Wire, 2024.The internal cable specification's reach of up to 1 m on SFF-TA-1016 connectors; the external specification's 2 m on SFF-TA-1032.
  18. [18]Disaggregating the Data Center: Designing Remote Gen5 NVMe Arrays with MCIO — HighPoint Technologies (a retimer card maker), 2026.The claim that passive Gen5 MCIO hits a wall at 30 cm. No measurement is given.
  19. [19]Will a long MCIO cable cause speed attenuation? — JMTJM (a cable maker), 2026.The claim that a passive Gen5 MCIO cable is generally limited to 0.5 to 0.75 m. No measurement is given.
  20. [20]MCIO 85 Ω x8 x16 vertical receptacle (product brief) — TE Connectivity, 2022.The connector maker's positioning: SlimSAS, SlimSAS LP and MCIO for SAS and PCIe Gen4/Gen5, with the 85 Ω MCIO stated to support PCIe 5.0 at 32 Gbps and SAS-4 at 24 Gbps.

Connector and series names on these pages — JST, Molex, Micro-Fit, Mini-Fit, PicoBlade, Pico-Lock, CLIK-Mate, PCIe, MCIO, SlimSAS, OCuLink, HSD, HFM and DEUTSCH among them — may be trademarks of their respective owners. They are used only to identify the connectors an assembly is built with or mates with. Interconnix is not affiliated with, sponsored by or an authorized distributor of any connector maker. PCI Express, PCIe and CopprLink are trademarks of PCI-SIG.

Need a custom MCIO or SlimSAS assembly at this length? Send your spec to support@interconnix.com.

Length, gauge, connector part numbers and the generation it has to run at are enough to start; a drawing or the host's loss budget is better. The quotation says what is built and what is sourced.